Preventing scan-based attacks on secure-ICs with on-chip comparison

Hardware implementation of secure applications, e.g. cryptographic algorithms, is subject to various attacks. In fact, it has been previously demonstrated that scan chains introduced by Design for Testability open a backdoor to potential attacks. Here we propose a scan-protection scheme that provides testing facilities both at production time and over the course of the circuit’s life. The underlying principle being to scan-in both input vectors and expected responses and compare expected and actual responses within the circuit. Compared to regular scan tests, this technique has no impact on the quality of the test or the modelbased fault diagnosis. It entails negligible area overhead and avoids the use of an authentication test mechanism.